Automatically assigned DDC number: 00435

Manually assigned DDC number: 00435

Title: Determining the Idle Time of a Tiling

Author:

Author:

Author:

Subject: Karin Hogstedt,Larry Carter,Jeanne Ferrante Determining the Idle Time of a Tiling

Description: This paper investigates the idle time associated with a parallel computation, that is, the time that processors are idle because they are either waiting for data from other processors or waiting to synchronize with other processors. We study doubly-nested loops corresponding to parallelogram- or trapezoidal-shaped iteration spaces that have been parallelized by the wellknown tiling transformation. We introduce the notion of rise r, which relates the shape of the iteration space to that of the tiles. For parallelogram- shaped iteration spaces, we show that when r Gamma2, the idle time is linear in P , the number of processors, but when r Gamma1, it is quadratic in P . In the context of hierarchical tiling, where multiple levels of tiling are used, a good choice of rise can lead to less idle time and better performance. While idle time is not the only cost that should be considered in evaluating a tiling strategy, current architectural trends (of deeper memory hierarchies and multipl...

Contributor: The Pennsylvania State University CiteSeer Archives

Publisher: unknown

Date: 1997-08-22

Pubyear: 1997

Format: ps

Identifier: http://citeseer.ist.psu.edu/140249.html

Source: ftp://ftp.cs.ucsd.edu/pub/carter/shape.ps

Language: en

Rights: unrestricted

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