Automatically assigned DDC number: 621381548

Manually assigned DDC number: 621381548

Number of references: 4

Title: An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis

Author:

Author:

Subject: Srinivas Devadas,Kurt Keutzer An Algorithmic Approach To Optimizing Fault Coverage For BIST Logic Synthesis

Description: Most approaches to the synthesis of built-in self test (BIST) circuitry use a manual choose-and-evaluate approach, where a particular BIST generator is chosenandthen evaluatedby faultsimulating the design with the vectors that the chosengenerator generates. We develop an algorithmic synthesis-during-test approach in this paper, wherein the tasks of synthesizing the BIST logic and directed test pattern generation (DTPG) are intertwined to maximize the resulting fault coverage. Our approach is applicable to a variety of BIST strategies including those that use linear- and nonlinear-feedback shift registers. We show how our method can be used to synthesize LFSR polynomials, LFSR seeds, LFSR weights, nonlinear feedback, or bit-fixing logic. Experimental data is presented. I. INTRODUCTION Built-in Self Test (BIST) has been of interest for some time because it provides in-field testing at request and simplifies fault diagnosis. Recently, with the cost of high-speed VLSI testers increasing wi...

Contributor: The Pennsylvania State University CiteSeer Archives

Publisher: unknown

Date: 1998-07-02

Pubyear: 1998

Format: ps

Identifier: http://citeseer.ist.psu.edu/147238.html

Source: http://caa.lcs.mit.edu/~devadas/pubs/bist.ps

Language: en

Relation:

Relation:

Relation:

Relation:

Rights: unrestricted

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