Automatically assigned DDC number: 00433

Manually assigned DDC number: 00433

Number of references: 35

Title: Timed Automata

Author:

Subject: Rajeev Alur Timed Automata

Description: . Model checking is emerging as a practical tool for automated debugging of complex reactive systems such as embedded controllers and network protocols (see [23] for a survey). Traditional techniques for model checking do not admit an explicit modeling of time, and are thus, unsuitable for analysis of real-time systems whose correctness depends on relative magnitudes of different delays. Consequently, timed automata [7] were introduced as a formal notation to model the behavior of real-time systems. Its definition provides a simple way to annotate state-transition graphs with timing constraints using finitely many real-valued clock variables. Automated analysis of timed automata relies on the construction of a finite quotient of the infinite space of clock valuations. Over the years, the formalism has been extensively studied leading to many results establishing connections to circuits and logic, and much progress has been made in developing verification algorithms, heuristics, and too...

Contributor: The Pennsylvania State University CiteSeer Archives

Publisher: unknown

Date: 1999-03-16

Pubyear: 1999

Format: ps

Identifier: http://citeseer.ist.psu.edu/203146.html

Source: http://www.cis.upenn.edu/~alur/Cav99.ps.gz

Language: en

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