Automatically assigned DDC number: 00422

Manually assigned DDC number: 00422

Number of references: 32

Title: Balancing Computation and Memory in High Capacity Reconfigurable Arrays

Author:

Subject: Stylianos Perissakis Balancing Computation and Memory in High Capacity Reconfigurable Arrays

Description: Reconfigurable arrays have been used to speed up computational tasks, some times achieving orders of magnitude of improvement either in cost/performance or raw performance. An integral part of such systems is a significant amount of memory, distributed among multiple reconfigurable chips. The current scaling trend of VLSI technology, that allows packing of more and more gates on a single silicon die, tends to throw such architectures out of balance, unless significant amount of memory is integrated on the die, close to the processing elements. Embedded DRAM technology, integration of dynamic RAM with logic circuits on the same chip, offers a unique opportunity to balance the processing and memory resources in large reconfigurable chips. In this thesis I evaluate the potential ...

Contributor: The Pennsylvania State University CiteSeer Archives

Publisher: unknown

Date: 2000-05-13

Pubyear: 2000

Format: ps

Identifier: http://citeseer.ist.psu.edu/330575.html

Source: http://www.cs.berkeley.edu/~sper/dissertation.ps.gz

Language: en

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